Numerous integrated circuit devices, structures and techniques of fabricating same, are known to the prior art. The following prior art patents and summaries are submitted to generally represent the state of the art.
Reference is made to U.S. Pat. No. 3,600,651 entitled "Bipolar and Field Effect Transistor Using Polycrystalline Epitaxial Deposited Silicon" granted Aug. 17, 1971 to D. M. Duncan.
Reference is made to U.S. Pat. No. 3,648,125 entitled "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure" granted Mar. 7, 1972 to D. L. Peltzer.
Reference is made to U.S. Pat. No. 3,730,786 entitled "Performance Matched Complementary Pair Transistors" granted May 1, 1973 to H. N. Ghosh.
Reference is made to U.S. Pat. No. 4,103,415 entitled "Insulated-Gate Field-Effect Transistor with Self-Aligned Contact Hole to Source or Drain" granted Aug. 1, 1978 to J. A. Hayes.
Reference is made to U.S. Pat. No. 4,157,269 entitled "Utilizing Polysilicon Diffusion Sources and Special Masking Techniques" granted June 5, 1979 to T. H. Ning.
Reference is made to U.S. Pat. No. 4,159,915 entitled "Method For Fabrication Vertical NPN and PNP Structures Utilizing Ion-Implantation" granted July 3, 1979 to N. G. Anantha.
Reference is made to U.S. Pat. No. 4,160,991 entitled "High Performance Bipolar Device and Method for Making Same" granted July 10, 1979 to N. G. Anantha et al.
Reference is made to the IBM Technical Disclosure Bulletin publication entitled "Complementary Bipolar Device Structure" by J. J. Chang et al., June 1974, Volume 17, No. 1, pages 21 and 22.
Reference is made to the IBM Technical Disclosure Bulletin publication entitled "Thin-Base Lateral PNP Transistor Structure" by G. C. Feth et al., December 1979, Volume 22, No. 7, pages 2939 through 2942.
The present trend in semiconductor technology is toward large scale integration of devices with very high speed and low power performance. The parameters that are essential to such high performance bipolar transistor are low parasitic capacitances as realized by (a) shallow vertical junction structure and (b) small horizontal geometry. To achieve these goals it is necessary to make the devices in the integrated circuits as small as possible.
With the advance in semiconductor processing technologies, such as in the fields of ion implantation, deep dielectric isolation, electron beam and x-ray lithographies, reactive ion etching, advanced insulator and polysilicon deposition techniques, and metal lift-off processes, fabrication of the ultra-high performance integrated circuit devices can be achieved.
Ion-implantation provides a means for precisely controlling the total amount of impurity transferred to the wafer. The impurity depth distribution is accurately controlled by implant energy. Unlike the conventional thermal diffusion process ion implantation is not a high temperature process. Thus, by using photo-resist or metal masking, multiple impurity introduction operations can be achieved without resort to high temperatures. A final thermal drive-in diffusion is sufficient to anneal out the radiation damage caused by implantation, and obtain desired device junction depth. Consequently, integrated circuit devices can be made shallower, with greater precision of the impurity distribution using ion implantation technology.
As the semiconductor devices become shallower, it is desirable to reduce the overall junction area so as to reduce parasitic capacitance. Further reduction of device parasitic capacitance can be achieved by shrinking of device horizontal dimensions and using dielectric isolation. Dielectric isolation is a method of fabricating integrated circuits in which the device components are isolated by other than P-N junctions. A well known dielectric isolation namely "Recessed Oxide Isolation" (ROI) is a commonly used process in present day semiconductor technology. Using Si.sub.3 N.sub.4 as the oxidation barrier, the ROI technique is done by etching grooves into the semiconductor wafer adjacent those regions in which PN junctions are to be formed. The silicon exposed by the grooves is then thermally oxidized to form recessed oxide regions providing dielectric isolation. The problem associated with the ROI is the formation of "bird's head" and "bird's beak" structure at the lateral edges of recessed oxide. The bird's head is undersirable because it can cause breaks or discontinuities in thin films covering the steps. The indefiniteness of bird's beak structure reduces the available active surface area and, therefore, imposes the need for wider tolerance of lateral dimension in the integrated circuit layout. A newly developed oxide isolation called "Deep Dielectric Isolation" (DDI) avoids the above mentioned ROI problem. The DDI process utilizes reactive-ion etching (RIE) to form deep narrow trenches into the wafer surrounding those regions in which devices are to be formed. [Reference is made to U.S. Pat. No. 4,104,086, entitled "Method For Forming Isolated Regions of Silicon Utilizing Reactive Ion Etching" granted Aug. 1, 1978 to J. A. Bondur et al., and U.S. Pat. No. 4,139,442 entitled "Reactive Ion Etching Method For Producing Deep Dielectric Isolation in Silicon" granted Feb. 13, 1979 to J. A. Bondur et al., respectively assigned to the assignee of the subject application]. The trenches are overfilled with SiO.sub.2 put down by chemical vapor deposition (CVD) technique. The overfilled SiO.sub.2 also planarizes the device surface. A blanket RIE back-etching to the semiconductor surface yields deep oxide isolation trenches. Unlike the bird's beak in ROI structure, sidewall of the DDI structure is nearly vertical. The surface of DDI regions and the silicon where devices are to be formed are coplanar. With the DDI, doping process for various device regions is then self-aligned by oxide isolation. The self-aligned process eliminates precise mask alignment steps and also saves a number of mask steps in the device fabrication.
As mentioned above the DDI enable us to form devices with considerably smaller cell size than those formed by using either P-N isolation or by ROI. Further reduction of device horizontal dimensions requires the use of high resolution capabilities of lithography and etching processes. The electron beam lithography is the most promising method for delineating submicron size device patterns. For device window opening the reactive ion etching (RIE) is the most attractive alternative of the conventional wet solution etching. The RIE is a dry process having directional etching characteristic. The etched device windows preserve the lithography defined etch mask dimensions, and the openings have vertical sidewalls. Thus, the E-beam lithography and reactive ion etching are compatible for fabricating very small device geometries.
For the very small bipolar transistor devices, as for example, micron size transistors, the base areas and, therefore, the collector-base parasitic capacitance is the most significant performance parameter. In the bipolar transistor the active base area is the region below the emitter. In the conventional transistors, fabricated by the prior art, the base contacts are formed above the inactive base area surrounding the emitter. The transistor base area that is needed to accommodate the emitter and base contacts is considerably larger than the active base area. To reduce the base area for making ultra-high performance bipolar transistors, a different approach in making base contact is desirable.
While the fabrication of complementary pairs of transistors on a common semiconductor substrate is highly desirable, the various efforts directed to producing complementary pairs of transistors have not been wholly successful. It would be desirable to provide complementary pairs of transistor devices on a common semiconductor substrate wherein each transistor (NPN and PNP) has high performance characteristics.
The invention is directed to the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements.
The most common technique for producing high speed logic circuits is the integration of NPN and PNP transistors within the same chip. Generally, a vertical NPN and a lateral PNP are used. The vertical NPN can be made very small in basewidth, as has been shown in prior art. An example of techniques for optimization of a vertical NPN is disclosed and claimed in the afore-identified Horng et al. U.S. Pat. No. 4,303,933 where the structure has a narrow basewidth, small junction area and a highly conductive polysilicon area surrounding the device which greatly reduces base resistance values. Commonly lateral PNP's are defined by lithographic masking techniques which must limit the basewidth to being either very wide (such as two micrometers or greater) or extremely variable. Another problem associated with junction isolated PNP's is that a large part of the emitter current is lost to the substrate. The combination of these effects results in low gain (for example, five or less) for lateral PNP devices.
In accordance with the invention, the aforerecited problems for the lateral PNP are solved by having the basewidth made smaller by using a controllable chemical vapor deposition (CVD) process to determine the basewidth. The problem of current injection into the substrate from the emitter and collector regions is obviated by the presence of an oxide isolation below these regions.